The present invention is well suited for both memory and logic technologies. However, for the purposes of discussion, it will be presented in terms of its applicability to Dynamic Random Access Memory (DRAM) technology. As the demand for more semiconductor memory, per chip, has increased, the methods for forming capacitors in DRAM technology have been rapidly evolving. DRAM technology has been and continues to be very well suited for addressing the increasing demand for more storage bits per chip area. However, a number of fundamental limitations have been posing increasingly greater challenges for the continued evolution of DRAMs, as the device dimensions for this popular technology have progressed deeper into the sub-micron regime. The unit memory cell of a DRAM chip is largely comprised of a single MOS transistor and a single storage capacitor, where the transistor is used as a transfer gate for reading as well as for forcing the charge state of the storage capacitor. The storage capacitor is a critical element of the storage cell. The information state of the memory cell, is determined by whether the stored charge on the storage capacitor is sufficiently above or below a given threshold level. Therefore, proper care must be taken to insure that once the storage capacitor is charged sufficiently above the threshold level, the charge will remain sufficiently above the threshold level until the memory state is deliberately changed by forcing the value of stored charge sufficiently below the threshold level. For example, DRAMs must utilize refresh cycles to compensate for a gradual loss of charge due to leakage current paths, wherein the state of the charge on the storage capacitor is periodically read and then restored (refreshed) back to the nominal value, corresponding to that state. Further more, the amount of stored charge must be sufficiently high, such that a somewhat predictable loss of charge due to a random collision from a high energy particle, such as an alpha particle, will not result in an erroneous information state. Accordingly, the storage capacitance values in DRAM cells cannot be arbitrarily scaled down along with other device dimensions. On the contrary, DRAM designers must maintain a certain minimum value of storage capacitance, in spite of the demand to reduce the amount of surface area that is taken up by the storage capacitor. This has led to innovative storage capacitor structures, where the amount of electrode area lost, by needing to reduce horizontal dimensions, is made up by extending the electrode area in the vertical direction. In addition, increasingly thinner dielectrics have been used to obtain higher values of capacitance per unit area in order to permit desired reductions in electrode area. Unfortunately. as reduced dielectric thickness values have begun to drop down into the tens of angstroms range, the associated adverse impact on yield and reliability, as well as the onset of non-negligible tunneling currents, have tended to impose a fundamental limit on continued reductions in dielectric thickness. This has partly been responsible for the development of advanced stacked dielectric structures made from relatively high dielectric materials, including silicon oxynitride and silicon nitride, in order to obtain increased capacitance per unit area values, relative to dielectric structures employing only silicon oxide as a dielectric.
U.S. Pat. No. 5,455,204 to Dobuzinsky, et. al., teaches a method for forming three-dimensional storage capacitor structures where the dielectric layer is composed of a thin uniform silicon oxynitride film. Uniformity problems, associated with trying to use chemical vapor deposition processes to fill narrow cavernous three-dimensional capacitor electrode structures with dielectric material are overcome by utilizing sequential rapid thermal processing in conjunction with a series of gaseous atmospheres. The end result is a highly uniform thin oxynitride layer which yields good overall electrical properties.
U.S. Pat. No. 5,523,596, to Ohi, et. al., teaches a method for forming a thin dielectric stack, for the formation of storage capacitors, consisting of a bottom silicon oxynitride layer, an overlying silicon nitride layer and a further overlying silicon dioxide layer. This method is taught as an improvement over oxide-nitride-oxide stacks, where the bottom oxide (sometimes a native oxide) tends to become too thick during the heat up time for the formation of the overlying nitride layer. To avoid this problem, the native oxide is first converted to a silicon oxynitride layer. by means of rapid thermal processing in an atmosphere of ammonia. The overlying nitride film is formed by low pressure CVD and the top oxide layer is formed by thermally oxidizing the top portion of the nitride layer in an atmosphere including water vapor. However, similar to Dobuzinsky, et. al., above, this invention does not seem to be particularly applicable for addressing the need for a single CVD process which can be readily tailored for various dialectic constants.
U.S. Pat. No. 5,616,401, to Kobayashi, et. al., teaches a method for forming a silicon oxynitride layer (with a changing composition in the growth direction) and an overlying silicon nitride layer, for the specific purpose of suppressing the well known bird's beak extension during Local Oxidation of Silicon (LOCOS) processing that is often used for electrical device isolation. During the CVD process for the oxynitride layer, the gas composition is gradually changed such that the property of the lower portion is close to silicon dioxide and the property of the upper portion is close to silicon nitride. The lower oxide portion is used to minimize stress at the interface with the underlying silicon while the upper nitride portion is used to provide a diffusion barrier to oxygen for minimizing the bird's beak extension.
U.S. Pat. No. 5,618,747, to Lou, teaches a method for forming a thin oxide-nitride-oxide stack, in conjunction with a polysilicon electrode structure, where the polysilicon deposition temperature is optimized for maximum polysilicon surface roughness. Maximum polysilicon surface roughness is used to obtain increased effective electrode area and, therefore, increased values of capacitance per unit of horizontal electrode area. The method for forming the ONO stack uses three process steps, which are presumed to be rather compatible with a relatively rough polysilicon surface. Again, similar to the above prior art, the complexity and the intent of the solutions that are provided do not appear to be particularly applicable to the need addressed by the present invention. Namely, the need for a one step process, for a thin storage capacitor dielectric that could replace a two step oxide-nitride process, whereby increased capacitance per unit area values could be adjusted while also maintaining a constant film thickness.